Presently, there is a great demand for shrinking semiconductor devices to provide an increased density of devices on the semiconductor chip that are faster and consume less power. The scaling of devices in the lateral dimension requires vertical scaling as well so as to achieve adequate device performance. This vertical scaling requires the thickness of the gate dielectric to be reduced so as to provide the required device performance.
On the other hand, there are several instances on a semiconductor chip where thicker gate dielectrics are still desired. For example, if the operating voltage is decreased, the device may no longer be compatible with most of the existing packaged integrated circuits which operate at a standard voltage. For, instance, most circuits using CMOS transistors with gate lengths of 0.5 microns or more operate at 3.3 V. When the gate length is decreased to 0.35 microns, the gate oxide thickness is reduced as well and the operating voltage is lowered to 2.5 V or lower in order to maintain reliability of the gate oxide. Thus, a device may be needed that has input/output peripheral sections that operate at 3.3 V so that the device may be used in systems using other chips operating at 3.3 V while allowing other internal portions of the device to operate at 2.5 V for improved performance. Other situations desiring dual gate dielectric thicknesses include: DRAMs in which a different gate dielectric thickness is desired for the high performance periphery versus the low leakage/low off-current array transistors; and embedded DRAMs which desire different thicknesses for transistors of the logic portion than for the DRAM transistors.
One prior art method for obtaining dual gate oxide thicknesses is called "split-gate". In one "split gate" process, an initial oxide is grown followed by photolithographically masking areas where thick oxides are desired, then etching the grown oxide in areas where the thin oxide is required. The photoresist is then removed via a clean-up process that may include ashing and a final oxidation is performed to grow the thin oxide and slightly thicken the oxide already grown in the thick oxide areas. One of the primary drawbacks of this approach is a higher defect density (resulting in low yield) for the thin gate oxide due to exposure to resist and exposure of the resist removal chemicals to the silicon surface.
Another prior method for forming dual gate oxide thicknesses uses a thin silicon nitride layer to protect the first gate oxide during the patterning and pattern removal for forming the second gate oxide. The thin silicon nitride layer may be removed either before or after the second gate oxide formation. However, the silicon nitride removal has a high probability of damaging neighboring material which can lead to the degradation of device performance and reliability. If the silicon nitride is removed prior to second gate oxide formation, the silicon substrate may be damaged and if the silicon nitride is removed after the second gate oxide formation, the second gate oxide may be damaged.